Sampling logic in UVM monitor : on all the clocks

In reply to chr_sue:

Thank you chr_sue. my BRAM spec does require continuous reads. I will look into it further.

Probably the problem is with SV modellingv or the way, driver is coded.
But most of the code/flow i have referred for UVM driver too is almost the same. Was wondering if i missed to go through any specific uvm topics. Please provide me the links, if so.