Sampling conditions for cross-coverage

SystemVerilog
,
1

I have a cover group like below (assume A and B are vector wires):

covergroup test_covergroup @(cover_grp_cond);

coverpoint_one : coverpoint A iff (cover_pt_cond_one);
coverpoint_two : coverpoint B iff (cover_pt_cond_two);

cross_one_two: cross coverpoint_one, coverpoint_two;

endgroup
test_covergroup = new;

What is the expectation on sampling for the cross cross_one_two? Will it be sampled only when cover_grp_cond is satisfied or is it sampled when all three of cover_grp_cond, cover_pt_cond_one and cover_pt_cond_two are satisfied? Any help is appreciated.

PS: I looked through the LRM, but I didn’t seem to find anything specific.

2

In reply to ajayramesh:

There is only one sampling trigger for a covergroup from the cover_grp_cond event. During the sample, coverpoint expressions get matched with bin values. When the iff condition is false, the coverpoint is ignored, and there can be no matching bin, hence no matching cross bin.

3

In reply to dave_59:

Thank you @dave_59. From what you’re saying, it looks like there would be a (small?) performance benefit to qualifying the cross also with (cover_pt_cond_one && cover_pt_cond_two).

Thank you for taking time and clarifying!!