Hi,
My question: is it possible to sample a clock signal of same frequency as sampling clock in assertions with $rose?
Well I tried but it’s not working, but instead of $rose we used:
property p1;
@(posedge clk1) (t1) ##0 (@(posedge clk2) 1) |-> t2 =$time;
end property
// clk1 = clk2
In reply to ramandeepk:
This question was addressed at
https://verificationacademy.com/forums/systemverilog/assertion-check-signal-toggling-or-not
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
In reply to ben@SystemVerilog.us:
but I just want to ask that is it so that $rose,$changed,$stable any of the system tasks doesnt work for same sampling and master clocks.i.e when clk1= clk2.
property test;
@(posedge clk1) $rose(clk2) |-> (t1 == $time) //wont work
$changed
$stable
In reply to ramandeepk:
$rose,$changed,$stable any of the system tasks doesn’t work for same sampling and master clocks.i.e when clk1= clk2.
With the property below, it is always vacuous when clk1= clk2 because @(posedge clk1)the sampling of clk2 is always ZERO, thus at every cycle there is no change.
property p_rose;
realtime t;
@ (posedge clk1) ($rose(clk2), t=$realtime) |-> ($realtime==t);
endproperty
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit osc, clk1, clk2, a, c;
realtime period =10ns;
initial forever #(period/2) osc=!osc; // oscillator
property p_c;
realtime t;
@ (posedge clk1) (1, t=$realtime) |-> @ (posedge clk2) ($realtime==t);
endproperty
ap_c: assert property(p_c) $display("time:%t assertion passed ", $time);
else
$display("time: %t assertion failed ", $time);
property p_rose;
realtime t;
@ (posedge clk1) ($rose(clk2), t=$realtime) |-> ($realtime==t);
endproperty
ap_rose: assert property(p_rose) $display("time:%t ap_rose assertion passed ", $time);
else
$display("time: %t aproseassertion failed ", $time);
initial begin
bit va;
#20;
$display("clk1 and clk2 INSYNC");
repeat(10) begin
va=1'b1;
@(osc);
clk1 <= osc;
if (va) clk2 <= osc;
else #1 clk2 <= osc;
end
$display("-----------------------");
$display("clk1 and clk2 OUT OF SYNC");
repeat(10) begin
va=1'b0;
@(osc);
clk1 <= osc;
if (va) clk2 <= osc;
else #1 clk2 <= osc;
end
$stop;
end
endmodule
# time: 250 assertion passed
# time: 350 assertion passed
# time: 450 assertion passed
# time: 550 assertion passed
# -----------------------
# clk1 and clk2 OUT OF SYNC
# time: 650 assertion passed
# time: 760 assertion failed
# time: 860 assertion failed
# time: 960 assertion failed
# time: 1060 assertion failed
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr