In reply to chr_sue:
chr_sue, thanks for your reply.
Will go through the link.
Here are my questions, appreciate if you could clarify:
- Right now i am doing module level verification of an up-down counter. Is it required to have reset handling on environment side? Eventually I would move to TOP level verification. Is it recommended to do the reset(on the fly) handling at chip level? what is the usual industry practice?
- If I decide to not to handle on-the-fly reset for module level verification, I still need to have a initial reset, right? Is it recommended to have this reset generation in top file or in driver? Is it that, generating it at Driver may help to align the reset with reset phase? Any leads to see the flow/example?
- If reset generation in in top file, its usually done in initial block, right?
- In case of reset handling at chip level, what is the best practice. I do see many links online.
- I will go through the above link you have sent. Hopefully it clears some of my questions.