In reply to susdesai:
It looks like you want to implement a complete UVM testbench. You can do this from scratch or using a UVM FRamework generator like the one from Doulos. Please see here:
https://www.doulos.com/knowhow/sysverilog/uvm/easier/
In reply to susdesai:
It looks like you want to implement a complete UVM testbench. You can do this from scratch or using a UVM FRamework generator like the one from Doulos. Please see here:
https://www.doulos.com/knowhow/sysverilog/uvm/easier/