Hello All,
I have to sample address only once while valid is asserted for multiple clocks , push it into the queue and remove when clear is asserted.
logic [7:0] valid;
logic [31:0] addr [7:0];
logic [7:0] clr_valid;
Here valid is multibit and is asserted for more then one clock cycle and with that addr[i] is also latched. When clr_valid comes(clr_valid is asserted only for one clock), valid gets de-asserted and then addr is dont care.
To sample addr and put it into queue through monitor, i used below code but I was thinking if any better way to do it, would be great.
confusion is that , here valid is multi bit and asserted for multi clocks. if it was only one bit i can easyly rely on @(posedge valid ) and sample address. since here valid is multi bit, i was not sure how to sample it in uvm_monitor. any better suggestion for below monitor_addr task ?
to clear it, its simple as clr_valid is asserted for just one clock.
in interface file, i flopped valid.
monitor_if
logic [7:0] valid_f;
always_ff @(posedge clk) valid_f <= #1ps valid;
UVM monitor :
task monitor_addr();
forever @(posedge clk) begin
for(int i=0 ;i <8 ; i++) begin
if(!vif.valid_f[i] && (vif.valid[i] !== valid_f[i])) begin
mon_port.write(addr[i]);
end
end
end
endtask
task clear_addr();
forever @(posedge vid.clk) begin
for(int i=0 ;i <8 ; i++) begin
if(vif.valid[i] !== clr_valid[i]) begin
mon_port_clear.write(addr[i]);
end
end
end
edndtask
endtask
Thank you.