I’m running the example from the book “A Practical Guide to Adopting the … (UVM)” second edition.
I’m running example 8-4.
I am compiling and running using VCS version H-2013.06-SP1_Full64
I compile with this command:
vcs -full64 -debug_all -sverilog +incdir+{UVM_HOME} -timescale=1ns/1ns +acc +vpi +define+UVM_OBJECT_MUST_HAVE_CONSTRUCTOR {UVM_HOME}/src/dpi/uvm_dpi.cc -CFLAGS -DVCS ${UVM_HOME}/src/uvm.sv ex8-4_layered_sequences.sv
No errors or strange warnings.
I then run with this command:
./simv +UVM_VERBOSITY=UVM_HIGH +UVM_OBJECTION_TRACE -gui
The simulation does not appear to run. I don’t see messages printing from the sequences. I see messages like this being generated:
UVM_INFO /home/apps/synop/vcs/H-2013.06/etc/uvm-1.1/base/uvm_phase.svh(1500) @ 0: reporter [PH/TRC/WAIT_PRED_OF_SUCC] Phase ‘common.build’ (id=73) *** No pred to succ other than myself, so ending phase ***
UVM_INFO /home/apps/synop/vcs/H-2013.06/etc/uvm-1.1/base/uvm_phase.svh(1500) @ 0: reporter [PH/TRC/WAIT_PRED_OF_SUCC] Phase ‘common.connect’ (id=85) *** No pred to succ other than myself, so ending phase ***
UVM_INFO /home/apps/synop/vcs/H-2013.06/etc/uvm-1.1/base/uvm_phase.svh(1500) @ 0: reporter [PH/TRC/WAIT_PRED_OF_SUCC] Phase ‘common.end_of_elaboration’ (id=97) *** No pred to succ other than myself, so ending phase ***
What’s going on? This is supposed to work out of the box on all simulators, right?
Thanks.