Rounding Errors in Delay Statements

SystemVerilog
,
1

I’m trying to generate plusarg-dependent clocks using conditional assigns and I’m getting rounding errors. Here’s the code sequence:

   `timescale 1ns/1ps

   initial begin
      fpga_80mhz_lvcmos = 1'b0;
      forever begin
         #6.25ns fpga_80mhz_lvcmos = ~fpga_80mhz_lvcmos;
      end	
   end
   assign clk80mhz = fpga_80mhz_lvcmos; // This WORKS correctly even when the `timescale is omitted and timescale resolves to 1ns/1ns 
...
   $printtimescale(); // FYI this prints 1ns/1ns regardless of the `timescale above
...
   initial begin
      forever begin
         if (!uvm_hdl_force("tb_top/dut/mclk_lim", fpga_lim_lvcmos)) begin
            `uvm_fatal("tb_top", $sformatf("Error! Failed to force LASER mclk_lim signal!"))
            break;
         end
         #((laser_25x ? 0.250ns : laser_10x ? 0.625ns : 6.250ns)) fpga_lim_lvcmos = ~fpga_lim_lvcmos; // This does NOT work, when laser_10x is 1 the time delay is rounded up to 1.
      end
   end

I also tried setting delays by multiplying a real value * 1ns, same results. Any ideas why this is happening?

2

I ‘solved’ this issue by using timeunit in the module; However, I’m not clear about the persistence of this setting.

3

In reply to mchal9thou:

Hard to answer because you did not show key fragments of code. The
`timescale compiler directive only applies to modules that follow the directive in a compilation unit. If you put it in the middle of a module, it has no effect until the next module.

The
timeunit construct takes precedence over compiler directives. When placed at the beginning of a module, it only applied to that module and has no effect on later modules.