$rose and $onehot

SystemVerilog
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1

1.what is the difference between $rose and onehot 2.what is the meaning of the following (signal === 4'b1111)[*1:]

2

In reply to suresh M:

$rose is system function used to access the sampled value of a given expression.

it is used in this way:

$rose(expression)
It will return true if the least significant bit of the expression changed from 0 to 1.If not ,it returns false.

For example:

  1. $rose(req) returns true if req[0] changes from 0 to 1 .
  2. $rose(ack) returns true when the rising edge of ack occurs. (ack is one bit signal)

…$fell (req) does the opposite.

$onehot is one of SVA build-in system functions.

it is used in this way:

$onehot(expression)

It checks that the expression is one-hot, which means that only one bit of the given expression can be high on a given clock edge.

For example:
$onehot(req) returns true if req == 4’b0100 (or 4’b1000 or 4’b0010 or 4’b0001)
returns false otherwise.

(signal === 4’b1111)[*1:$]

=== is known as case equality (!== case inequality) operator. It returns true (1-bit 1)or false (1-bit 0).This operator also considers the matches of the x and z bits in the operands.
The can’t be synthesized.

[*1:$] this is a consecutive repetition with indefinite timing window.

(signal === 4’b1111)[*1:$] means that the expression “signal === 4’b1111” should repeat itself anywhere between 1 to indefinite times.
In other word, it should be true consecutive anywhere between 1 to indefinite times.

we can expand this like:
(signal === 4’b1111) or
(signal === 4’b1111) ##1 (signal === 4’b1111) or
(signal === 4’b1111) ##1 (signal === 4’b1111) ##1 (signal === 4’b1111) or
…

[*] is a consecutive repetition operator
“$” is an eventuality operator. When used in the upper limit of the timing window (right hand side), this means that there is no upper bound for timing.

Hope this helps.