$root access from within packages is not allowed

SystemVerilog
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1

Hi

In my SV env I have the below code
`define MY_DEF $root.u1.u2.u3
This code is placed in one of the sv packge .
I compile the package first and then the top tb in which u1.u2.u3 is present. If I use questasim 10.1d I do not get this error message but if I use questasim 10.2c I am getting the error message “$root access from within packages is not allowed.”

I know hierachical access is a bad way of coding the env , but it has been done for some back door acess . I cannot afford to change the env now but want to use the same env with 10.2c version .

Can you please suggest some solution here ?

2

Two possible solutions:

  1. Define the env class and any parent classes that contain the env class in a module. Then you will be able to put hierarchical references in those classes. You might be able to put just put the env class in a module by registering it with the factory and having your test class use create_component_by_name() to construct the env.
  2. You can use an abstract/ class, or better yet inheritance classes introduced in 1800-2012, to create an API used to access the back doors you need.
3

I am already doing as you explained in point 1 in your reply and trying to do some hierarchical acess from class, this access is put in a class and included in a package. but tool does not like this… by adding -permissive to vlog I got rid of this problem…

4

In reply to polinkooran:

Can you explain the behavior of “tool does not like this”? Does it make a funny noise?

5

Yes it makes the funny noise and the noise is “$root access from within packages is not allowed.”
But when I add -permissive to vlog (10.2c and above versions) tool does not make this noise.