ROM design for BIST

SystemVerilog
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1

I am working with built-in self test technique. Can you please guide me to design a ROM block to store the response of C432 benchmark circuit.

2

In reply to ASHA PON:

This s a very general question without knowing how much design knowledge you already have. You might get some better resources to answer your question by asking it here.

3

Thank you sir. I am trying to write Verilog code to store 2^36 outputs of C432 benchmark circuits in ROM. It is taking more than 3 days to write all the address, still I have not completed the code. Can you please guide me whether my approach is correct or not. If not, can you suggest me to shorten the code.