In reply to cgales:
Thanks for cgales’s kindly help, my sequence item, axi_rd_seq, virtual sequence code is as follows,
//axi_transfer.sv
class axi_rd_transfer extends uvm_sequence_item;
rand bit[`AXI_ADDR_WIDTH-1 :0] araddr;
... ...
rand bit[`AXI_ID_WIDTH-1 :0] arid;
... ...
`uvm_object_utils_begin(axi_rd_transfer)
... ...
`uvm_field_int(arid, UVM_ALL_ON)
... ...
`uvm_object_tuils_end
//constraints as following, here not constraint arid
... ...
endclass
//axi_rd_seq_lib.sv :
class axi_read_seq extends axi_base_rd_seq;
rand int burst_num;
rand bit [1:0] row_addr_sel;
rand bit [1:0] master_arid;
function new(string name = "axi_read_seq");
super.new(name);
endfunction
task body();
for(int i=0; i< burst_num; i++) begin
`uvm_do_with(req, {req.araddr[20:19] == row_addr_sel;
req.arid[7:6] == master_arid;}) //line 82
end
endtask
endclass
//the following is virtual sequence
class axi_rd_after_wr_vseq extends axi_base_seq;
... ...
axi_read_seq axi_rd_seq_0_1;
... ...
`uvm_object_utils(axi_rd_after_wr_vseq)
function new(string name="axi_rd_after_wr_vseq");
super.new(name);
endfunction
virtual task body()
... ...
axi_rd_seq_0_1 = axi_read_seq::type_id::create("axi_rd_seq_0_1");
... ...
fork
... ...
`uvm_do_on_with(axi_rd_seq_0_1, p_sequencer.axi_read_seqr_0_1, {axi_rd_seq_0_1.burst_num ==`d100;
axi_rd_seq_0_1.row_addr_sel == 2'b01;
axi_rd_seq_0_1.master_arid == 2'b01;})
... ...
join
endtask
endclass