Reset : Control the number of transactions

UVM
1

Consider uvm_sequence

class my_sequence extends uvm_seqeunce #(packet);

int num_of_trans;

`uvm_object…

function new…

virtual task body;

req = packet::type_id::create(“req”);

for (int i=0; i<3; i++) begin

start_item(req);

assert (req.randomize()) with (req.wr_en==1);

finish_item(req);

num_of_trans++;

end

endtask

//In above, I am sending three WRITE transactions…

Driver code, will look something like this…

virtual task run_phase(uvm_phase phase);

forever begin

seq_item_port.get_next_item(req);

drive_reset;

drive_packet;

seq_item_port.item_done();

end

endtask

Question: For all three transactions, both reset and normal packet will be driven.

But the requirement is, only for the first transaction, reset should be driven.

In the remaining two transactions, reset should not be driven.

Inside the driver, I do not have control of num_of_trans.

How to use a variable " num_of_trans " which is present in the sequence to control the reset_task in the driver so that this will be driven only in the beginning?

I found two options, let me know your opinion on this.

=================

option1: declare a variable "num_of_trans" inside sequence_item, so that it can be used in driver like this

seq_item_port.get_next_item(req);

if (req.num_of_trans==0) begin

drive_reset;

end

drive_packet;

seq_item_port.item_done();

option2: sequence is an uvm_object, where the driver is a component.

To communicate between object and component, do I need to use p_sequencer?

If this is the preferred option, could you please point an example?

Thank You,

2

Why is reset being driven for every transaction received? I would expect that the driver only drives reset at the beginning, prior to processing any transactions:

virtual task run_phase(uvm_phase phase);
  drive_reset;
  forever begin
    seq_item_port.get_next_item(req);
    drive_packet;
    seq_item_port.item_done();
  end
endtask