In reply to naaj_ila:
I wanted to write an assertion in which
- When Reset goes from 1 to 0, ElecIDle=1
2.From there EleIdle should be 1 till Reset=0,It should not change in between
On your 2nd requirement, you most likely mean
"2.From there EleIdle should be 1 till another fall(Reset),It should not change in between
initial begin // Needed to create only ONE assertion
wait($fell(Reset));
ap_reset2idle: assert property(@(posedge clk)
$fell(Reset) |-> ElecIDle[*1:$] ##1 $fell(Reset));
end
// Typical application of reset, from my 4th Edition SVA book
module m10_19; // /ch10/10.19/m10_19.sv m10_19.png
bit clk, reset_n, system_ready;
default clocking cb_clk @ (posedge clk); endclocking
initial begin
wait(system_ready); // You need to assess the need for this.
a1: assume property( // you can also use assert property
##1 $rose(reset_n) |-> always reset_n);
// The ##1 is needed to detect the $rose
end
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115