Requirement for Assertion to Fail

SystemVerilog
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1

Hi ,

Consider a 4-state variable used in an assertion . I was wondering what’s the requirement for the assertion to Fail ?

I have following Code :: EDALINK

Can I say if the variable / result of expression has bits as X / Z / 0 the assertion Fails .
However if any bit is 1 the assertion Passes

2

In reply to hisingh:

if the variable is 2’bX1 the possible values for ‘x’ are 0, z, 1
Thus, the values 2’b01 2’bz1 2’b11 are not 0