Hello!
I relation to this question here regarding svverification I would like to ask the following complementary question.
So, let’s assume a non-mixed language simulation. Reading this technote reference in the question linked above, can I assume that the license features qhsimvl or msimhdlsim allow me to simulate any SystemVerilog / UVM 1.2 class without the need for svverification as long as nothing in my simulation explicitly uses the functions listed in the technote?
Regards,
CW