Request - Acknowledge related Assertion

SystemVerilog
,
7

In reply to ben@SystemVerilog.us:

Thanks for the reference . Will look into them .

Have a final question related to the original question I posted


property ack_req ;
 
   (  ( ack[->1] )  or  ( $rose( req ) [ -> 1 ] )  )  |-> 
 
   if( ack )   
 
   ( 1 , $display(" TIME : %0t  ACK  True  " , $time ) )   //  Added  for  Debugging  !!  
 
   else   
 
   ( 1'b0 )  ;
 
  endproperty 
 
  property  req_ack ;
 
    @( posedge clk )  $rose( req )  |=>  ack_req ;
 
  endproperty

  c_property : cover   property ( req_ack )  $display(" TIME : %0t  REQ_ACK  PASS " , $time ) ;

  initial  forever  #10 clk = ! clk ;

  initial  begin
 
// ' req '  is  True  on  1st  posedge  N  then  ' req ' is  de - asserted  just  before  Next  posedge .
//  ' req '  is  Asserted  at  TIME : 69  .  ' ack '  is  asserted  at  TIME : 49  !!
 
 
       #9 ;  req = 1 ;    //  TIME:9
 
      #20 ;  req = 0 ;    //  TIME:29
 
      #20 ;  ack = 1 ;    //  TIME:49

      #20 ;  req = 1 ;    //  TIME:69
 
       #5 ;
    $finish() ;
 
  end

I Observe O/P as ::

TIME : 50 ACK True
TIME : 50 ACK True
TIME : 70 ACK True
TIME : 70 ACK True
TIME : 70 REQ_ACK PASS

[ Q ] Why does the assertion Pass at TIME : 70 instead of TIME : 50 ?

Antecedent ( ack[->1] ) is true at TIME : 50 hence I expect assertion to Pass at TIME : 50