Folks,
I am looking for examples of assertions used in actual designs.
I took a cursory look at the cores available at GitHub/freecores but I haven’t seen any assertions here.
Any pointers in this regard is highly appreciated.
In reply to verif_learner:
Please look at the Open Verification Language (OVL).
In reply to cgales:
In reply to verif_learner:
Please look at the Open Verification Language (OVL).
cgales,
Thanks. I have used OVL regularly for my projects.
However, my request is a bit different.
I would like to get a list of assertions typically used in projects.
For example, for my design, I might have say a few thousand of assertions identified.
Now, these could be implemented using a few hundred assertion libraries.
I am interested in the actual assertion identified for few sample designs.
I hoped that some of the designs at free cores would come along with assertions but whatever I have sampled don’t have it.
Many formal verification vendors have implemented a library of assertions for specific cores.
In this forum, users have expressed complex designs pieces that need assertions. In my book, I borrowed many of these postings into a chapter to demonstrate types of problems.
I created a package
https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
It addresses the use of dynamic delays and repeats.
SVA Alternative for Complex Assertions paper addresses complex assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
On a personal basis, unless you have a core or standard interface,
I believe that using a library of assertion is combersome and can lead to errors.
I prefer to write direct properties/assertions without argunents, unless reusability is needed. This makes the review process much easier.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy