input [11:0] foo;
always @ (
foo [0] ||
foo [1] ||
foo [2] ||
foo [3] ||
foo [4] ||
foo [5] ||
foo [6] ||
foo [7] ||
foo [8] ||
foo [9] ||
foo[10] ||
foo[11]
) begin
// do something
end
How can I replace the code above with something simpler?
Thank You!
In reply to Brian Jensen:
always @(foo) isn’t an option, since this is part of an interface.
dave_59
4
In reply to new_to_uvm:
Why don’t you give us some more code so we know what your options are?
Why does being part of an interface prevent you from using always @(foo)?
And why not
always_comb
begin
//do something
end
Yes, being part of an interface should not be a problem.
Try the piece of code in edaplayground.com.
Copy-Paste the code below in the testbench pane.
interface my_if();
logic [11:0] foo;
endinterface
module tb;
my_if _if();
dut d0 (_if);
always @ (_if.foo)
$display ("[TB] foo = 0x%0h", _if.foo);
initial begin
#10 _if.foo = 12'h4ef;
#20 _if.foo = 12'h31a;
#10 _if.foo = 12'h0;
end
endmodule
Copy-Paste the code below in Design Pane
// Code your design here
module dut (my_if _if);
always @ (_if.foo)
$display ("[DUT] foo = 0x%0h", _if.foo);
endmodule
Hope this helped.
There are more examples on this site: SystemVerilog Tutorial