Hello All,
Please help me to understand how we can achieve the polymorphism in systemverilog without virtual keyword.
Thanks in advance
Regards
Sunil.
There are two kinds of polymorphism in SystemVerilog, static and dynamic. Parameters give you the static, and virtual methods give you the dynamic. Please see my DVCon paper: Using Parameterized Classes and Factories: The Yin and Yang of Object-Oriented Verification