Repeat Loop Not Working

SystemVerilog
,
1

I have a repeat look as below.
There is no compile error. But I don’t see any display

   real a;
    a = 5.0;
    repeat(5.0) begin
      #1;
      $display("Wassup at %t",$realtime);
    end

But when i have

    repeat(5.0) begin
      #1;
      $display("Wassup at %t",$realtime);
    end

I get the 5 displays.

But there is no compile error in the first case. Why is that repeat doesn’t take real numbers

2

In reply to abhiram.b:

It would help to add two lines giving us a complete example.

module top;
  initial repeat(5.0) begin
      #1;
      $display("Wassup at %t",$realtime);
    end
endmodule

This gives me 5 lines on every simulator I tried.

3

In reply to dave_59:

Hi Dave I ran your code on Icarus verily simulator 0.10 on edaplayground and dint get any display when i used real number.
But when i used a decimal 5, i got 5 displays

I got the same result on a Cadence simulator

4

In reply to Jack Bryan:

I tried it on 5 different simulators and got 5 displays. I guess you found a tool bug.