Advice for addressing two issues with the UVM register model.
I modeled my registers using the UVM register model. I was using the VCS simulator/Synopsys tools for this testbench. My implementation was fully functional, however I had to overcome two issues and I wonder whether whether I made correct choices in overcoming the issues.
Issue 1: In the UVM adapter class I was required to define functions bus2reg and reg2bus to translate a register read/write request into a bus specific request. I noticed that the arguments to reg2bus was a “struct” (not a transaction class). This eliminated my ability to pass the register transaction to the bus driver along with additional information required to complete the transaction (in my case the additional information consisted of register specific timeout for the access). Since specifying a register specific timeout was a necessity in my testbench (not a luxury), I opted to bypass the adapter all together. In order to pass a register transaction to my agent, I simply look up the register’s sequencer in the register’s uvm_map class, I pass the transaction directly to the agent via the sequencer and let the agent execute it, and obtain the response in case of a read. A wonderful side effect of doing this was that I gained complete control of the blocking/non-blocking nature of the register request to the agent, rather than being at the mercy of the register model for the timing of the register access.
What I did not resolve is how to explicitly call uvm mirroring functions so that the register mirror is maintained.
Issue 2: When I passed transactions throught the UVM adapater class, my testbench hung somewhere in the UVM classes whilst waiting on read data to get back to the sequence. I traced the hang for several days without resolution. When I bypassed the UVM adapter and used the register’s sequencer directly, the hang was eliminated.
In a nutshell: I think a testcase or testbench environment has much more direct control and visibility of a register access if the UVM adapater is not used. (Caveat: I haven’t yet determined how to update register mirrors explicity in the register access. Also I haven’t yet determiend how to implement backdoor accesses explicity when the adapter is bypassed).