Register model initial values

UVM
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3

In reply to chr_sue:

Hi,

thanks for replying. This piece of code is in the body of my test sequence and it is executed after calling


super.body()

My test sequence is a derived class from a class which is, in turn, derived from uvm_reg_sequence:

  • uvm_reg_sequence
  • - my_parent_seq
    [list]
    - my_seq


    [/list]

The code of my_parent_seq is simply:


class my_parent_seq extends uvm_reg_sequence;
  `uvm_object_utils(my_parent_seq)

  my_reg_model regmodel;

  // Sequencer
  my_uvc_sequencer p_sequencer;

  function new(string name = "");
    super.new(name);
    set_automatic_phase_objection(1);
  endfunction: new

  virtual task body();
    assert($cast(p_sequencer, m_sequencer));
    assert($cast(regmodel, p_sequencer.cfg.regmodel));
  endtask: body

endclass: my_parent_seq

What I’ve noticed is that the values returned by get() are updated to the actual value only after a physical read, which is not would I would expect.

Here’s a practical example:

  • I have a register with default (reset) value 0x03fc;
  • the two LSBs are associated to a field;
  • I change the value of that field to 3:

temp_reg = my_regmodel.reg_blk.get_reg_by_name("my_region.my_reg");
temp_field = temp_reg.get_field_by_name("my_field"); temp_field.set( 3 );
temp_reg.update(status); assert(status == UVM_IS_OK);

At this point, I am expecting the generated transaction to write 0x03ff to the register, instead it writes 0x0003.
The only way to get 0x03ff is to read the register first.

Another note: the UVM test reg_all passes I guess just for the reason that the first set of accesses is a read of the complete register map to perform the reset value sub-test.

Is all of this expected?
Am I really supposed to physically read the complete register map to have a consistent model?
Thanks in advance for any help.