Hello Forum,
I am verifying the protocol interface using UVM-1.1d and QuestaSim-10.2b.
Could you please help me to resolve the following doubt:
class clk_gen extends uvm_component;
`uvm_component_utils(clk_gen)
REG_BLOCK rb;
virtual cmi_if intf;
task run_phase (uvm_phase phase);
clk_gen();
endtask : run_phase
task get_current_mach();
if(rb.inst_tx_mode.get() == 2) // Getting error here. Here, "inst_tx_mode" is the register defined in the "REG_BLOCK"
begin
...
...
end
endtask
task clk_gen();
...
get_current_mach(); // Here we are calling the above task.
...
endtask
endclass :clk_gen
Here the error i am getting is:
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 46 Process: /pkg::clk_gen::clk_gen/#FORK#75_fe2d7ba File: clk_gen.sv
# Fatal error in Task pkg/clk_gen::get_current_gear at clk_gen.sv line 42
- Do i need to define build_phase to create the “rb” object and config_db to get the interface.
Please help and suggest.
Thanks and Regards
Sunil S.