In reply to umagraman:
Hi,
You can take multiple register map instances and configure them for a number of required interfaces. you can refer the following document for multiple register map ([Click here…])(Section : RAL register map and adapter)
Also, find answers inline.
a) Should I have 3 instances of the reg model and connect them to the three different sequencers?
Answer:- Yes, For each bus, a sequencer is required to be configured.
b) If I write through one interface - say reg1 through IF1, how can I make sure the reg1 values will get reflected for the other interface also (since it is the same set of registers)
Answer:- Ideally, this should be your test criteria as the register is the same but access interface is different. You can write register with one register map and read_compare with other all register maps. (There is an inbuilt register sequence (uvm_reg_shared_access_seq) which you can use)
Regards,
Mitesh Patel