I’m very new to UVM and have spent a few weeks trying to get my head round the basics so I expect this will bethe first of many questions.
One thing I’m looking at is Register Abstraction Layer and to try an understand it what I decided to do is write all the register classes for all our registers in our current device.
I’m using Mentor’s Register Assistant and all seemed fine until I tried to understand how back door access was performed.
To cut to the chase the question I have is, how does UVM know where in the hierarchy the register lives and where is this specified?
The reason I believe it could be important is that I did all the classes for the registers - simple - and then treated our device as being ‘flat’ and simply specified the registers as being in the top block when doing the register block class, where as in reality they are a couple of levels down. The next question is do I need to specify the classes in a hierarchical manner that replicates the physical device hierarchy?
A little explanation of where I am…
I know VHDL and have, in the past, written simple VHDL test benches. For reasons I wont go into I’ve inherited a UVM SystemVerilog test bench that was originally written for another device but with identical interfaces (PCIe) to the one I’m adapting it for. I’ve never used SV or UVM previously so as you can see I’m faced with a massive task to get this test bench working as soon as possible.
I’ve spent about four weeks reading large sections of both the cookbook and the Accellera UVM User Guide (plus lots of on-line material) which has got me up and running firing packets at the device and using visual inspection to check what comes out. From what I can see the scoreboard is virtually redundant from looking at the code.
The next step I’ve identified is to get the scoreboard and self checking into the test bench and as seeing as all device output is a function of what you put in and a complicated set of internal registers I think I should write a register abstraction.
This is part of my answer but what is still unclear is how the works with hierarchy.
//
// Register configure method prototype
//
function void configure (
uvm_reg_block blk_parent,
uvm_reg_file regfile_parent = null,
string hdl_path = ""); // This is what I want
I’m thinking that I put the relative path to register in hdl_path and UVM works out the total path by looking at the register abstraction hierarchy???