Regarding simple immediate assertion

SystemVerilog
,
1

Hi,
I am trying following example of a simple immediate assertion:


     bit not_sig , sig ;
  assign not_sig = !sig ;

  always_comb  begin
     assert ( not_sig != sig )  $display("T:%0t Pass",$time);
                          else  $display("T:%0t Fails",$time);
  end

  initial  begin
    #4; sig = 1; 
    #4; sig = 0; 
  end

LRM 9.2.2.2 : The procedure is automatically triggered once at time zero, after all initial and always procedures have been started so that the outputs of the procedure are consistent with the inputs.

I have a few questions

(1) At time:0 does the always_comb block execute after assign statement ?

(2) Every time ‘sig’ changes , both always_comb and assign execute, does the LRM define a pre-defined order of execution between them ?

(3) One of the output I observe


      T:0 Pass
      T:0 Pass
      T:4 Pass
      T:8 Pass

How is it that there are 2 pass reports at time:0 ?

(4) Is there a possibility that always_comb executes before assign( whenever ‘sig’ changes ) so that the simple immediate assertion might fail ?

(5) Does the action block of a simple immediate assertion execute in the same region where the ‘assert’ statement executes ?
For the above code, could I state that the action block executes in Active region ?

2

In reply to Have_A_Doubt:

  1. The LRM does not specify, but it should not matter. Both always_comb and assign are guaranteed to evaluate at least once at time 0. A big problem with always @* is that it could miss events at time 0.
  2. Section 4.7 Nondeterminism explicitly says the order is not defined.
  3. That should not be happening with this example. In any case, you should be using deferred immediate assertions in combinational logic to prevent glitchy output. See section 16.4 Deferred assertions.
  4. It’s possible. Use a deferred assertion.
  5. The action block of an immediate assertion (non-deferred) takes place in the region where the always_comb block is executing; the active region.
3

In reply to dave_59:
I wrote a paper on immediate assertions. See the link in my signature below.
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Links_to_papers_books - Google Docs