Regarding sequence

SystemVerilog
,
1

hi
i am writing like:
in sequence:-

start_item(trans);
assert(trans.randomize() with {
trans.link[4].word==data[55:48];
trans.link[5].word==data[47:40];
trans.link[6].word==data[39:32];
trans.link[7].word==data[31:24];
trans.link[8].word==data[23:16];
trans.link[9].word==data[15:8];
trans.link[10].word==data[7:0];
finish_item(trans);

let’s say my data is of 120 bytes. and i am not willing to write it like above. i want it to generalize using some loop like foreach. so how many data bytes are there, i need not to worry about writing.

please guide

2

In reply to Er. Shipra:

linksize = trans.link.size()-1;
if (trans.randomize() with {
   foreach (trans.link[w]) trans.link[linksize-w].word==data[w*8+:7]; else `uvm_error()
finish_item(trans);
3

In reply to dave_59:

In reply to Er. Shipra:

linksize = trans.link.size()-1;
if (trans.randomize() with {
foreach (trans.link[w]) trans.link[linksize-w].word==data[w*8+:7]; else `uvm_error()
finish_item(trans);

it worked for me… thank you so much for your guidance and help.