In reply to cgales:
Hi cgales,Thank you for your response.
Already I made all these changes and tried even though it is not working in UVM1.2 and it is giving the same result as before.
Below i am sharing the code which i have modified, If any mistakes i did please let me know.
class packet_sequence extends uvm_sequence # (packet);
`uvm_object_utils(packet_sequence)
function new (string name = "packet_sequence");
super.new(name);
`uvm_info("packet_sequence",$sformatf("%m"),UVM_MEDIUM);
endfunction
task body();
`uvm_info("TRACE",$sformatf("%m"),UVM_MEDIUM);
`uvm_info("TRACE",$sformatf("%m 11111111111"),UVM_MEDIUM);
if (starting_phase != null)
begin
starting_phase.raise_objection(this);
end
repeat(5)
begin
req = packet::type_id::create("req");
`uvm_info("TRACE",$sformatf("%m wait grant"),UVM_MEDIUM);
start_item(req);
`uvm_info ("SEQ", $sformatf("start_item() fn call done"), UVM_MEDIUM)
req.randomize();
finish_item(req);
end
if (starting_phase != null)
begin
starting_phase.drop_objection(this);
`uvm_info("TRACE",$sformatf("%m 77777777777"),UVM_MEDIUM);
end
endtask
endclass
class test extends uvm_test;
`uvm_component_utils(test)
env e ;
packet_sequence p_seq;
uvm_sequencer #(packet) p_seqr0;
//uvm_factory factory;
//uvm_coreservice_t cs = uvm_coreservice_t::get();
function new(string name,uvm_component parent);
super.new(name,parent);
`uvm_info("test",$sformatf("%m"),UVM_MEDIUM);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_MEDIUM);
e=env::type_id::create("e",this);
p_seqr0 = uvm_sequencer#(packet)::type_id::create ("p_seqr0", this);
endfunction : build_phase
function void start_of_simulation_phase (uvm_phase phase);
super.start_of_simulation_phase(phase);
`uvm_info("TRACE",$sformatf("%m"),UVM_MEDIUM);
uvm_top.print_topology();
// factory.print();
endfunction : start_of_simulation_phase
virtual task run_phase(uvm_phase phase);
p_seq=packet_sequence::type_id::create("p_seq",this);
phase.raise_objection(this);
p_seq.start(p_seqr0);
phase.drop_objection(this);
endtask
endclass
class driver extends uvm_driver # (packet);
`uvm_component_utils(driver);
virtual add_sub_if vif;
function new(string name, uvm_component parent);
super.new(name,parent);
`uvm_info("drv",$sformatf("%m"),UVM_MEDIUM);
endfunction
function void build_phase (uvm_phase phase );
super.build_phase(phase);
uvm_config_db # (virtual add_sub_if) :: get (this, "", "add_sub_if",vif);
endfunction
task run_phase (uvm_phase phase);
super.run_phase(phase);
vif.a=0;
vif.b=0;
vif.doAdd=0;
forever
begin
//for the above line we are getting a cross module reference error .
`uvm_info ("DRIVER", $sformatf ("Waiting for data from sequencer"), UVM_MEDIUM);
seq_item_port.get_next_item(req);
`uvm_info ("DRIVER", $sformatf ("Getting data"), UVM_MEDIUM);
// @(negedge vif.clk);
send();
// this.print();
req.print();
//this.print();
// @(negedge vif.clk);
seq_item_port.item_done();
`uvm_info ("DRIVER", $sformatf ("Driver task done"), UVM_MEDIUM);
end
endtask
task send ();
vif.a<=req.a;
vif.b<=req.b;
vif.doAdd<=req.doAdd;
endtask
endclass
Result:
UVM_INFO driver.sv(43) @ 0: uvm_test_top.e.ag.drv [DRIVER] Waiting for data from sequencer
UVM_INFO packet_sequence.sv(7) @ 0: reporter@@p_seq [packet_sequence] $unit::\packet_sequence::new
UVM_INFO packet_sequence.sv(11) @ 0: uvm_test_top.p_seqr0@@p_seq [TRACE] $unit::\packet_sequence::body
UVM_INFO packet_sequence.sv(12) @ 0: uvm_test_top.p_seqr0@@p_seq [TRACE] $unit::\packet_sequence::body 11111111111
UVM_INFO packet.sv(20) @ 0: reporter@@req [packet] $unit::\packet::new
UVM_INFO packet_sequence.sv(21) @ 0: uvm_test_top.p_seqr0@@p_seq [TRACE] $unit::\packet_sequence::body wait grant
UVM_INFO packet_sequence.sv(7) @ 0: reporter@@packet_sequence [packet_sequence] $unit::\packet_sequence::new
UVM_INFO packet_sequence.sv(11) @ 0: uvm_test_top.e.ag.seqr@@packet_sequence [TRACE] $unit::\packet_sequence::body
UVM_INFO packet_sequence.sv(12) @ 0: uvm_test_top.e.ag.seqr@@packet_sequence [TRACE] $unit::\packet_sequence::body 11111111111
UVM_INFO packet.sv(20) @ 0: reporter@@req [packet] $unit::\packet::new
UVM_INFO packet_sequence.sv(21) @ 0: uvm_test_top.e.ag.seqr@@packet_sequence [TRACE] $unit::\packet_sequence::body wait grant
UVM_INFO packet_sequence.sv(23) @ 0: uvm_test_top.e.ag.seqr@@packet_sequence [SEQ] start_item() fn call done
UVM_INFO driver.sv(46) @ 0: uvm_test_top.e.ag.drv [DRIVER] Getting data
Name Type Size Value
req packet - @829
a integral 8 'h4
b integral 8 'h2
doAdd integral 1 'h1
begin_time time 64 0
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 38 uvm_test_top.e.ag.seqr.packet_sequence
sequencer string 22 uvm_test_top.e.ag.seqr
UVM_INFO driver.sv(55) @ 0: uvm_test_top.e.ag.drv [DRIVER] Driver task done
UVM_INFO driver.sv(43) @ 0: uvm_test_top.e.ag.drv [DRIVER] Waiting for data from sequencer
UVM_INFO packet.sv(20) @ 0: reporter@@req [packet] $unit::\packet::new
UVM_INFO packet_sequence.sv(21) @ 0: uvm_test_top.e.ag.seqr@@packet_sequence [TRACE] $unit::\packet_sequence::body wait grant
UVM_INFO packet_sequence.sv(23) @ 0: uvm_test_top.e.ag.seqr@@packet_sequence [SEQ] start_item() fn call done
UVM_INFO driver.sv(46) @ 0: uvm_test_top.e.ag.drv [DRIVER] Getting data
Name Type Size Value
req packet - @846
a integral 8 'h3
b integral 8 'h1
doAdd integral 1 'h1
begin_time time 64 0
depth int 32 'd2
parent sequence (name) string 15 packet_sequence
parent sequence (full name) string 38 uvm_test_top.e.ag.seqr.packet_sequence
sequencer string 22 uvm_test_top.e.ag.seqr
UVM_INFO driver.sv(55) @ 0: uvm_test_top.e.ag.drv [DRIVER] Driver task done
UVM_INFO driver.sv(43) @ 0: uvm_test_top.e.ag.drv [DRIVER] Waiting for data from sequencer
UVM_INFO packet.sv(20) @ 0: reporter@@req [packet] $unit::\packet::new
UVM_INFO packet_sequence.sv(21) @ 0: uvm_test_top.e.ag.seqr@@packet_sequence [TRACE] $unit::\packet_sequence::body wait grant
Execution interrupted or reached maximum runtime.
Done