Regarding Race Condition

SystemVerilog
11

In reply to NC22:

module DUT(input bit clk, int A,
           output int B);
  always @(posedge clk) begin
    B <= A + 1;

  end
endmodule

module testbench;
  int a,b;
  bit clk;
  DUT dut(.clk,.A(a),.B(b));
  initial #5 repeat(100) #5 clk = ! clk; // posedge clk at 10,20,30,...
  
  initial begin // avoiding race
    @(posedge clk)
    a <= 1; // using NBA
    @(posedge clk)
    a <= 3; // using NBA
    @(negedge clk) //using negedge
    a = 5;         // NBA does not matter
    @(negedge clk) //using negedge
    a = 7;         // NBA does not matter
  end
endmodule