Regarding port mismatch between VHDL and SV

SystemVerilog
1

VHDL unconstrained array equivalent in system verilog.
situation:
Here i need drive the VHDL inputs from SV testbench.

Example:
VHDL unconstrained array:
type type_name is array (type range <>) of element_type
equivalent in System verilog.

2

A dynamic array or queue in SystemVerilog has the equivalent functionality of an unconstrained array in VHDL. However, you will need to check the user manual of your tool as there may be restrictions in connecting ports of these types.

3

In reply to dave_59:

Thanks for quick reply.
when i tried with queue, i am getting mismatch between number elements in svport and VHDL port
Here i am attaching the code:

VHDL (type) [used in design]
type t_z is record
x: integer range 0 to 1023;
y: integer range 0 to 1023;
end record;

type t_z_array is array(integer range <>) of t_z;

type t_z_array is record
t_z_array: t_reg_roi_configuration_array(7 downto 0);
end record;

z_array: t_z_array;

System verilog equivalent (used in testbench)
typedef struct {
int x;
int y;
} t_xy;

typedef struct {
t_xy xy_array [$];
} t_z;

typedef struct {
t_z z_array ;
} t_z_array;

t_z_array z_array;

when i am connecting these VHDL z_array port and SV z_array port , above mentioned error is giving by cadence irun simulator during elabaration.

thanks.

4

In reply to Mallikarjun79:

small mistake in earlier reply (corrected here)

when i tried with queue, i am getting mismatch between number elements in svport and VHDL port
Here i am attaching the code:

VHDL (type) [used in design]

type t_z is record
x: integer range 0 to 1023;
y: integer range 0 to 1023;
end record;

type t_z_array is array(integer range <>) of t_z;

z_array: t_z_array (7 downto 0);

System verilog equivalent (used in testbench)
typedef struct {
int x;
int y;
} t_xy;

typedef struct {
t_xy xy_array [$];
} t_z;

typedef struct {
t_z z_array array;
} t_z_array;

t_z_array z_array;

when i am connecting these VHDL z_array port and SV z_array port , above mentioned error is giving by cadence irun simulator during elaboration.

thanks.