Thanks Dave.
I tried runnning this piece of code on Questa-64 10.1b
module constr_test();
class parent;
rand int unsigned a;
constraint c1{
(a < 10);
}
endclass
class child extends parent;
rand int unsigned a;
constraint c2{
(a > 10);
}
endclass
parent parent_handle;
child child_handle = new();
initial
begin
parent_handle = child_handle;
parent_handle.randomize();
$display("a = %d",parent_handle.a);
end
endmodule
As per the LRM, I am supposed to get a value > 10 for a(as the constraint in the child class overrides the inherited constraint). But I end up getting a value < 10 for a which is in line with the constraint defined in the parent class.
VSIM 15>run -all
#a = 4