Regarding Method Overriding / Polymorphism SystemVerilog

In reply to Anand Kumar C.R:

Constraint blocks are virtual, meaning when the constraint block in derived class has the same name as parent class, it would get override. I have modified the code, which works for your requirement !!

module polym_cons();
class parent;
rand int unsigned a;
constraint c1{
(a < 10);
}
endclass

    class child extends parent;
      constraint c1{
        (a > 10);
      }
    endclass

    parent parent_handle;
    child child_handle = new();

    initial
    begin
      parent_handle = child_handle;
      parent_handle.randomize();
      $display("a = %d",parent_handle.a);
    end

endmodule