Regarding memory allocation of an object in SV

In reply to sureshreddi:

Thanks For your explanation.

I have one more doubt i.e

if the above code is changed to

In System Verilog;-

class A;

int a=10;
int b =20;

task disp()
$display(“This is Parent Class”);

endclass

class B extends class A;

int c = 30;
int d = 40;

task disp()
$display(“This is child Class”);

endclass

Program main

initial
begin
A A1;
B B1;
B1 = new();
A1=B1;
$display(B1.a);
$display(B1.c);

OUTPUTS:

10
30

Pls correct me if output results are wrong

My doubt is

Is it possible to access the base class properties and methods using child class handle(i.e $display(B1.a)).

If the above statement is correct then pls find the below code.

In System Verilog;-

class A;

int a=10;
int b =20;

task disp()
$display(“This is Parent Class”);

endclass

class B extends class A;

int a = 30;
int b = 40;

task disp()
$display(“This is child Class”);

endclass

Program main

initial
begin
A A1;
B B1;
B1 = new();
A1=B1;
$display(B1.a);

What is the output.

30 or 10

$display(B1.a); ------> how child class handle choose the base class properties of variable ‘a’ and child class properties of variable ‘a’.