In verilog we refer a variable through its name in a particular module.so, if we have 2 variables of same name it’s a conflict so that may be the reason they made it a sytax error in verilog.
Coming to sytem verilog we refer a variable in a class through the handle of that object.
Parent class doesn’t have any idea regarding the properties of Child class.So no conflict while accessing variable “a” with A1 handle and when accessing with Child class object it refer to local variable “a” than the parent class variable.
Whatever you declare a variable in extended class is local to that class and not visible to base class so there is no conflict here.
Logically there is no conflict in declaring same variable name in parent as well as child class.
let’s see any expert will present his view.