Regarding LRM Section :: Cross bin set expression

SystemVerilog
,
1

Hi All ,

LRM Section 19.6.1.4 has the following code =>


//  Modified from the Original Code in LRM 
 bit [2:0]  a  , b ; 
   covergroup cg_exp ;
     aXb : cross a, b
     {   
        bins one = '{ '{1,2}, '{3,4}, '{5,6} };   
     }   
   endgroup

I observe that 65 bins are generated , not sure why ? .
My expectation was out of 8 x 8 i.e 64 cross products as 3 combinations are specified via bins one ,
So I expected 62 Total bins out of which 61 are auto bins retained

Also the LRM discuses about CrossValType and CrossQueueType within cross types which I didn’t quite get .
Any suggestions on when and why should one use them ? What are advantages of using them ?

2

In reply to Have_A_Doubt:

This particular feature of a cross is a late addition to SystemVerilog and not widely supported. You may want to discuss with your tool vendor directly.

CrossValType and CrossQueueType are typedefs local to the cross that help user define functions that are also local to the cross instead of manually writing the literal patterns as in your example.

3

In reply to dave_59:

Hi Dave ,

This particular feature of a cross is a late addition to SystemVerilog and not widely supported.

I do observe limited support for it across the simulators I tried this on .

As you previously mentioned in Automatic_bin_retention_in_cross ::

Explicit cross bins are for merging or ignoring bins.

bin ’ one ’ doesn’t follow this . Any suggestions why ?

The LRM doesn’t mention the total bins that would be created in this particular section unlike the other sections .