Regarding hdl path for UVM RAL

UVM
,
1

Hey,

I am trying to use backdoor methods for uvm RAl.
Can anyone please help to set the hdl path for it.
I have attached the link for the code.

2

In reply to riddhi:

5 things to add:
(1) you have to set the ‘add_hdl_path_slice’ for each register like this:
reg_mem_addr.add_hdl_path_slice(“reg_mem_addr”, 0, 32);
(2) The lock_model() is missing. This belongs to the register model. It si the last line of the build function of the register block;
(3) This is optional you can set the uvm_hdl_path for RTL and for GATE like this:
add_hdl_path(“tbench_top.DUT”, “RTL”);
(4) Be careful with th objections. Have it only in the test.
(5) Use peek and poke for backdoor.

3

Hi,

Thanks for reply.
But getting error related to hdl path.

UVM_ERROR: set: unable to locate hdl path (tbench_top.DUT.reg_intr)
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR: set: unable to locate hdl path (tbench_top.DUT.reg_intr)
Either the name is incorrect, or you may not have PLI/ACC visibility to that name

4

In reply to riddhi:

This is caused by your different namimg for the registers in the design and the testbecn. In the design the reg name is intr, control etc. and in the testbench you are using the names reg_intr etc. Alighn the naming and it will work.

5

Thank you so much for the help.
Now it working perfectly.

1 Like
6

can you help me out? i have the same error but still its not resolving

7

Could you please describe your problem in more detail?

8

UVM_ERROR: set: unable to write to hdl path (top.DUT.timer_0)
This is the Error, can please check my code.

9

Looks like you have a tool issue and it is a little bit strange. Even VCS comes to the correct end without reporting an ERROR in thge summary. But you have this ERROR in the logfile. Other simulators are working fine.

1 Like
10

yeah thanks