Regarding assertion property

UVM
, ,
1

Hi,
I am writing an assertion for one scenario . e.g There is an ALU which has one i/p port for data_in , i/p port for
command(instruction), reset , clk and one o/p port . I want to check the functionality for addition that if command = SUM then along with the command on the same edge data_in for first operand will be taken , then on the second edge second operand will be taken and after 3 clock cycles o/p will be observed.

Here is the assertion which I have written :

     property check_out_val(outval,writes,command); 
	      int  temp_data1,temp_data2;
	      @(posedge amd_apb_if.PCLK) disable iff(amd_apb_if.rst)
	    command |->  (!rst)(temp_data1 = writes) ##1  (temp_data2 = writes) ##3 (outval == (temp_data1 + temp_data2)) ;
	  
   endproperty	

   check_sum : assert property (check_out_val(amd_apb_if.PRDATA,amd_apb_if.PWDATA,amd_apb_if.command)) 
     else
	`uvm_error("CCHECK SUM VAL FAILED","sum value")

It’s giving me following Error :

Error-[SE] Syntax error
  Following verilog code has syntax error : 
token is '(' 
command |->  (!rst)(temp_data1 = writes) ##1  (temp_data2 = writes) ##3 (outval == (temp_data1 + temp_data2)) ;
        ^

Can I write the assertion the way I have written ?

2

In reply to Maitri@07:

I believe you want

property check_out_val(outval,writes,command);
   int  temp_data1,temp_data2;
   @(posedge amd_apb_if.PCLK) disable iff(amd_apb_if.rst)
	    command |->  (1,temp_data1 = writes) ##1  (1,temp_data2 = writes) ##3 (outval == (temp_data1 + temp_data2)) ;
 
   endproperty
3

In reply to dave_59:

Hi Dave,
Thank you for the quick reply . With your change it’s working now. I want to know the meaning of (**1,**temp_data1 = writes) . What does it mean ?

I had used another approach , too . In interface I had defined this property and instantiated transaction class as in transaction class I had defined two rand variables data1 and data2 . And then through transaction class handle I was assigning these ip datain values but It was giving me the error that dynamic variables can’t be accessed. Is there any way that we can access random variables defined in the class through interface or module ?