Reg Model Mirrored value doesn't change

UVM
1

Hi,

I have a simple reg model created in my UVM enironment.
When I do reg_a.write() or reg_a.read(), I can see the corresponding behavior in the waveform, which seems to be fine.
However I notice the mirrored value never get updated, which is not expected per my understanding.
I have tried front door write(), read(), set()+update(), written data got read back as expected.
But none of these methods would change the mirrored value, which is always 0.
The target register is a general purpose RW type register, nothing special.
What could be wrong in such case?

Thank you very much!

2

In reply to Renjie Lu:

Are you sure your reg_model is correct and also the inegration.
Could you please share some code?
Best would be to have it on Edaplayground.com

3

In reply to chr_sue:

Thank you for your response.
Looks like I have figured out the problem.
I haven’t implemented the explicit predictor, therefore I need to manually do reg_model.default_map.set_auto_predict(1) in order to do the automatic predict, which is OFF by default in UVM1.2.

With this change I can see the mirror value starts to change.