Referring to a property local variable from outside of property

SystemVerilog
,
6

In reply to ben@SystemVerilog.us:

Ben,

Thank you for the explanation and the details. It is infact getting terminating only when both the push data are same as the 2nd consequent is matched immediately at first pop only.

Just to check my understanding, I think the same issue (in case WRITE → WRITE → READ, assuming the first two writes are writing same data) would be seen in the clock domain assertion specified in one of the recent posts. We need to take a similar care for this assertion too. Correct?

property p_async_fifo; 
   bit[WIDTH-1:0] v_wdata; 
   @(posedge wclk) (!wfull && wen, v_wdata=wdata) |-> 
	@(posedge rclk) ##[1:$] !rempty && ren ##0 rdata==v_wdata; 
endproperty