Referring to a property local variable from outside of property

SystemVerilog
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4

In reply to ben@SystemVerilog.us:

Hello Ben,

Could you please help me understand how will the assertion started @t2 will fail at the completion of @t0 at time t=4? Are they not two independent active threads?

For assertion @t2, is the consequent check suppose to happen in the duration #[5:10]? i.e, at t=6 onwards?

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@t4, assertion started @t2 will fail if data0 != data2
This is because each of those 2 successfully attempted assertions will terminate.