Reference code for Out of Order pipelined driver

Can you please provide sample code? It would greatly help with understanding the concept. thanks.

In reply to hgandhi@gmail.com:

Well that may be too much to ask for on a forum, but since you’ve started - let’s try :-) Can you provide a simple, clear spec with signal names as a starting point? Don’t point us to AXI spec as no body expect AXI code to be shown here for free.

One of the emerging applications of a UVM trace is to be able to understand a protocol like what you are asking - first step is to create a set of timing diagrams to understand the protocol and then code the driver.

Regards
Srini
www.verifworks.com