Reference code for Out of Order pipelined driver

UVM
,
1

Can you please provide sample code? It would greatly help with understanding the concept. thanks.

2

In reply to hgandhi@gmail.com:

Well that may be too much to ask for on a forum, but since you’ve started - let’s try :-) Can you provide a simple, clear spec with signal names as a starting point? Don’t point us to AXI spec as no body expect AXI code to be shown here for free.

One of the emerging applications of a UVM trace is to be able to understand a protocol like what you are asking - first step is to create a set of timing diagrams to understand the protocol and then code the driver.

Regards
Srini
www.verifworks.com

3

Hi Srini,

Reopening the thread as I have the same doubt:
Below is the code. My doubt is if we use uvm_sequence_item and sen the response back to sequence from driver won’t that be out of order only ?

 `uvm_object_utils(my_seq_w_rsp)
 
  use_response_handler(1);
  transaction tr;
  int count;
  function new(string name = "my_seq_w_rsp");
   super.new(name);
  endfunction: new
  
  task body();
   tr = transcation::type_id::create("tr");
   start_item(tr);
    tr.randomize();
   finish_item(tr);
   reponse_handler();
  // get_response(tr);// --> this is blocking in nature therefore cannot be used in pipelined driver. Therefore, we will use use_response_handler to capture the number of responses.
  endtask: body

  
  function void response_handler();
   count++;
  endfunction: response_handler
endclass

//Driver code 


class my_bidir_driver_get_put extends uvm_driver#(transaction);
`uvm_component_utils(my_bidir_driver_get_put)


 transaction tr;
  virtual mem_if vif;
  function new(string name = "my_bidir_driver_get_put", uvm_component parent);
   super.new(name, parent);
  endfunction: new


  function void build_phase(uvm_phase phase);
   super.build_phase(phase);
   if(!( uvm_config_db#(virtual mem_if)::get(this, "", "vif", vif))
   `uvm_fatal(get_type_name(), "Virtual interface not get")
  endfunction  


  task run_phase(uvm_phase phase);
   tr = transaction::type_id::create("tr");
   forever begin //{
    seq_item_port.get(tr);
    vif.req <= 1;
    vif.addr <= tr.addr;
    vif.wr_en <= tr.wr_en;
    if(tr.wr_en == 1)
     vif.wdata <= tr.wdata;
     
    while(vif.ready != 1)begin 
     @(posedge vif.clk);
    end 
    $cast(rsp, req.clone());
    rsp.set_id_info(req);
    if(tr.wr_en == 0) begin //{
    tr.error = vif.error;
    tr.rdata = vif.rdata;
    vif.req <=0;
    end //}
    
    seq_item_port.put(tr);
   end //}
  endtask: run_phase
endclass: my_bidir_driver_get_put