Ref keyword

SystemVerilog
1

hello all
i am unable to understand the ref keyword is used in task and function. can anyone help me out what it is actually doing, and why we need that ?
thanks

2

In reply to Abhisek sarkar:

Maybe useful Link

Regards,
Mitesh Patel

3

In reply to Abhisek sarkar:
https://verificationacademy.com/forums/systemverilog/const-ref#reply-51090

4

In reply to dave_59:

Thanks sir i clearly understood my doubt.

5

In reply to dave_59:

Dave :
Can i assume the ref key word in SV is same as &(passing by reference &) in C/C++? as
void functionName( int &);

Thanks

6

In reply to VE:

yes.