Ref arguments in functions that have static lifetime

SystemVerilog
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13.5.2 Pass by reference
Arguments passed by reference are not copied into the subroutine area, rather, a reference to the original
argument is passed to the subroutine. The subroutine can then access the argument data via the reference.
Arguments passed by reference shall be matched with equivalent data types (see 6.22.2). No casting shall be
permitted. To indicate argument passing by reference, the argument declaration is preceded by the ref
keyword. It shall be illegal to use argument passing by reference for subroutines with a lifetime of static.
The general syntax is as follows:

subroutine( ref type argument );

For example, the preceding example can be written as follows:

function automatic int crc( ref byte packet [1000:1] );
for( int j= 1; j <= 1000; j++ ) begin
crc ^= packet[j];
end
endfunction

Why is the ref argument in a static function illegal? Is it because it is pointing to a memory location and the memory allocation happens during runtime?
I’m trying to gain some understanding on what is not available at for a static function to have a ref argument.
Thank you.

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In reply to natasv:

Before answering your question it needs to be said that there is no need for functions with static lifetimes. It’s only there because of legacy Verilog which did not have the concept of stack frames.

In a function with a static lifetime, its arguments are static variables and can be accessed from outside the function just like any other static variable. If you tried to access that argument before the function was ever called, that would create an illegal reference. Also, if you only access the argument after calling the function, after it returns you wind up with a static pointer to a variable reference.

The LRM could have gone in the direction of making it illegal to access static arguments passed by ref from outside the function, but they wanted to promote the use of functions with automatic lifetimes.

I suggest looking at my DVcon 2021 presentation The Life of a SystemVerilog Variable, particularly the section on subroutine lifetimes.