Hi, I’ve created an array of wires from the design. while running an operation on said array some signals when printed produce ‘x’ instead of ‘0’ or ‘1’.
here is some of the code as reference to my issue:
int error_detected;
logic signals[26];
logic expected_signals_init[26];
logic expected_signals_final[26];
logic expected_signals[26];
logic don't_care_array[26];
signals = {wire1, wire2...., wire26} //where the wires are connected to the design as follows: wire1 = `DESIGN_PATH.wire1;
for(int i = 0; i < signals.size(); i++) begin
automatic int j=i;
fork
#1ns;
begin: function_flow
$display("inside the function_flow thread %0d", j);
$display("signals value in index i, %0d", signals[j]);
if (!dont_care_array[j]) begin
//do logic here - includes disabling the timeout thread
end
begin: timeout_signals_array
#50us
`uvm_error((m_name, $sformatf("Timeout occured in signals array, index %0d", j))
end
join_any
end
so a few things:
what happens is some signals when printed don’t produce a valid value (such as mentioned ‘x’)
there is a second fork inside (where do logic is stated) which is not happening and I don’t understand why because I am destroying the timeout when we enter the logic part.
so my questions are:
- is it ok to create and use an array of signals from the design as I used?
- I don’t fully understand the relationship of threads in SystemVerilog - sometimes I use the #1ns to help the code work and sometimes doesn’t. does SystemVerilog produce different thread processes or is it 1 which is managed by the processor?
- is it ok to use if (signals[j] == 1) or something of the sort for logic purposes in a code? (relates to first question a little bit)
thanks for the help in advance!
*if the code tags didn’t work I am sorry, this is my first post and I wasn’t sure.