Real variables to vector

SystemVerilog
1

Hello,

From the top I have to send 2 real variables(topVar1, topVar2) to an interface which supports:
input real inputPort [2:1]
How can I call the interface from the top without declaring another array of reals in the top?

Thanks,
Bogdan

2

In reply to mavro:

Are you talking about a SystemVerilog
interface or a design interface? And the title of your post mentions a real going to a vector. But your description does not mention that at all.

Can you show some code, even if its the code you are trying to avoid?

3

Hello Dave,

It is about a SystemVerilog interface. Here is the code:

interface my_if(
input real inputPort [1:0]
);
endinterface : my_if

module top();
real topVar1, topVar2;
// TODO: How can I send the above real variables to the interface without creating a size of 2 vector of reals where I will add topVar1 and topVar2 ?
my_if my_inst_if(.inputPort(…)
);
endmodule : top

Best Regards,
Bogdan

4

In reply to mavro:
You can use an assignment pattern with arrays of any type.

module top();
  real topVar1, topVar2;
  my_if my_inst_if(.inputPort('{topVar1, topVar2})
  );
endmodule : top