Reading from file, File is updating at runtime

UVM
,
1

Hi I never worked with file i/o in system verilog. Currently my requirement is to read file which is updating at runtime. I tried many of the sv inbuilt file i/o related functions described in 1800-2012 and also surfed from many forums, But not found my requirement.

Scenario is, I need to read from a file which is updating at runtime (appending data) from other module (C Reference Model).

My file contains addr and data in a single line, separated by single space.

MyFile.txt


3 1234ba1
6 2345acf
2 95678fe
.
.
.

Reference module appending addr and data as I mentioned above…line by line.

I am using following code to separating out addr and data from my file whenever line is available…


initial begin
  bit fend;
  file = $fopen("MyFile.txt", "r");
  fend = $feof(file);

  fork
    forever begin
      // Waiting for new entry in file
      wait(fend);
      read_file = $fscanf(fd, "%h %h", addr, data);
    end
    forever begin
      // Updating fend bit
      #1 fend = $feof(file);
    end
  join
end

But this thing is not working… Can anyone pls help me in this.

2

You will need to explain more why you can’t let your C program finish writing to the file, and then start your simulation.

Inter-process communication (IPC) will be required if you cannot run the C program first, and that will be OS specific.

A better solution might be to integrate the C program using the SystemVerilog DPI and avoid communicating through a file.

3

In reply to dave_59:

My C-Reference model is running parallel with RTL.

From my SV testbench I am forwarding transaction (ex WRITE: Data and (x,y) Location) to RTL using dedicated interface and also at same time C Model is also getting same transaction using DPI connection. Now based (x,y) location value, both RTL and C Model are calculating Address and updating their MEMORY.

Now my main goal is, RTL is calculating and updating correct memory or not. C Model is giving me one file in which it is providing me Address and Data and based on that address I will reading RTL memory (backdoor access). And by the help of this file provided by golden C Reference model I can compare the data based on the address.

I can also check this after run_phase, but I need to know that Is it possible to fetch the data during file is still updating from other source? If it is possible then I will definitely go ahead with this approach.

4

In reply to electron:

You still need to explain further about how the C model is running parallel using the DPI connection. How are they running in different threads?

And the #1 delay in the forever loop is not an operating system clock delay.

5

In reply to dave_59:

In reply to dave_59:
You still need to explain further about how the C model is running parallel using the DPI connection. How are they running in different threads?

My mean of C model running parallel mean, My testbench is forwarding the transaction at runtime to my C Model as well as RTL. C Model is calculating based on the received transaction and give me back the response as per my transaction within zero time. So I can say, It is writing to MyFile.txt at zero time but with different different time.

In reply to dave_59:

In reply to dave_59:
And the #1 delay in the forever loop is not an operating system clock delay.

#1 delay, I’ve taken just for the ref. Clock delay has added at my real code.