Re-initialize objects without calling constructor

SystemVerilog
1

Hi,

I have a few associative arrays in my class 1.
class1 {
int assoc_arr1[int] = '{default:0};
}

I instantiate the class in another class 2.
In class 2 , there is a loop within which i update the associative arrays of class1.Obj.
eg:

//snippet of class 2 code 
task some_task;
@posedge clk:
for (int i = 0 ; i < Q_DEPTH ; i ++) begin
// some lines of code here
class1Obj.assoc_arr1[Q[i]]++;
end
some_Class1Queue.push_back(class1Obj);
endtask : some_task

Before entering the above for loop, i want to initialize all values of assoc_arr1.
Currently i am doing that by calling “new” after i enter the posedge clk block.
ie :

task some_task;
@posedge clk:
class1.Obj = new();
for (int i = 0 ; i < _DEPTH ; i ++) begin
// some lines of code here
class1Obj.assoc_arr1[Q[i]]++;
end
some_Class1Queue.push_back(class1Obj);
endtask : some_task

I feel that calling “new” every posedge clk would be a ‘time-consuming’ function call. [please correct me if i am wrong here].
How can i re-initialize my assoc_arr without calling the constructor and having a new object.

2

In reply to abisha:

I’m guessing by ‘time consuming’ you mean that it uses up run time. The first rule of optimization is “Don’t”. If you haven’t profiled your simulation and seen that this is a performance bottleneck, you shouldn’t try to optimize. This applies generally.

3

In reply to Tudor Timi:

thank you for your reply. and no i haven’t profiled my simulation , so probably i will drop optimizing this one like you have suggested.

4

turns out i can do a initialize like this ,

class1Obj.assoc_arr1 = `{default:0};

before entering the for loop.

for (int i = 0 ; i < _DEPTH ; i ++) begin
// some lines of code here
class1Obj.assoc_arr1[Q[i]]++;
end