Range width must be constant expression

SystemVerilog
, ,
1

I have the following function:

   function void foo_array_vec_bit (int seed, inout bit [31:0] q [$], input string mem_name, int_type curr_int_type,  int arr_size, const ref int vec_bit_size);
      bit [31:0] temp;       
      for (int i = 0; i < arr_size; i++) begin
	 foo_vec_bit(temp[0 +: vec_bit_size], seed+i, mem_name, vec_bit_size, curr_int_type);
	 q.push_back(temp);
      end	
   endfunction: foo_array_vec_bit

The call to the function is:

foo_array_vec_bit(seed, arr_vec_bit, "arr_vec_bit", t_data_bit, 9, arr_vec_b_size);

Where:

bit [31:0]   arr_vec_bit [$];
   int arr_vec_b_size = 9;

I got the folllowing error:
** Error: …\sv\base_transaction.sv(105): Range width must be constant expression.
line 105 is the call for foo_vec_bit.

2

Hi saritr.

temp[0 +: vec_bit_size], is the issue. You can not use syntax like this because it not allow to do slicing with the help of dynamic variable. I guess temp is output so you can directly take that as output . Const ref is not making is constant value. Actual use of const ref is const ref argument behaves the same as a ref argument, except that the compiler will treat the formal argument as read-only. There are a number of situations that require functions to have no side-effects (no modification of variables outside of the function except through the return value). So the LRM restricts functions in this situation to only having input or const ref arguments.

– CB Singh