I am trying to implement the following in systemverilog.
always_comb
begin
for(int i=0;i<=124;i=i+6)
begin
offset = DFF_data[ ((2*i)+1):(2*i) ]; // Error !
data_output[i+offset]= data_input[i];
end
end
I get the following error in the line marked above: Range must be bounded by constant expressions. I can see the error ocuurs beacuse of the use of “i” in defining the range of array DFF_data. But writing this without “i” seems impractical. I am using QuestaSim 10.1d. Has anyone come across such a situation?
data_in[7*(j+1)+j:8*j] // while i am doing this in sv this error comes----> Range must be bounded by constant expressions how to get the same functionality
It looks ssingh’s original intention was to add a working implementation choosing 2-bit out of the data: offset = DFF_data[ ((2*i)+1):(2*i) ];
So the equivalent should become: offset = DFF_data[ (2*i) +: 2 ];
instead of choosing only width=1 with: offset = DFF_data[ (2*i) +: 1 ];